Binning for Structured ASICs
The First practical binning for solution for ASICs
Speed-grading (binning for speed) has been offered on standard semiconductor ICs for decades. Even FPGAs which are field-customizable are offered at different performance levels, often providing up to a 35% increase in speed and selling at up to a 100% premium. But FPGAs are actually manufactured as standard components. Speed grading, however, has never been offered for mask-programmed ASICs. Structured ASICs (module-based ASICs configured with a small number of custom masks) are now becoming more popular every day due to high mask costs for SOC Standard Cell Devices. For Structured ASICs as well as traditional mask-programmed gate arrays, an opportunity now exists to offer speed grading for ASICs - for the first time.
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